Time Scaling: A System-Oriented New Paradigm for Post-Moore Semiconductor Development

1. The Historical Track and Bottleneck of Moore’s Law

Put forward by Gordon Moore in 1965, Moore’s Law has guided the semiconductor industry for over half a century. By geometrically scaling down transistor linewidth from 90nm, 28nm to the current 3nm and 2nm advanced nodes, the industry realized sustained performance improvement.

Nevertheless, continuous geometric miniaturization is gradually reaching physical boundaries. The investment cost of advanced process fabs has surged exponentially, thermal dissipation challenges become prominent, and the performance improvement brought by each new generation of process technology keeps diminishing. The whole industry is urgently seeking diversified sustainable innovation paths to meet the explosive growth demand of computing capacity from cloud computing, artificial intelligence and data centers.

2. Core Principle of Time Scaling Innovation

Time constant τ (tau) describes the required duration for electrical signals to switch status and transmit across circuits, which determines the response speed of electronic devices. Different from the traditional method of indirectly reducing τ by shrinking transistor size, time scaling regards the optimization of τ as the direct core goal of technological iteration.

It builds a multi-level collaborative optimization framework covering device, circuit, chip and system layers:

• At the device layer: Optimize the switching speed of single transistors and reduce parasitic resistance and capacitance of metal interconnects;
• At the circuit layer: Shorten critical signal transmission paths and streamline circuit layout design;
• At the chip layer: Optimize the collaborative scheduling of computing units, cache and on-chip networks to avoid invalid data migration;
• At the system layer: Upgrade inter-chip and server communication protocols to cut synchronization and waiting latency among multiple hardware devices.

This technical paradigm evolves from the System-Technology Co-Optimization (STCO) methodology widely adopted in the chip design field. By matching optimal manufacturing processes and interconnection technologies for different functional modules, the whole computing system can reach the best overall efficiency. Relevant theoretical research points out that systematic time scaling optimization is expected to deliver equivalent computing density performance matching 1.4nm advanced process nodes through architectural and system innovation.

3. Global Industrial Value and Cooperation Prospect

Time scaling reshapes the evaluation standard of semiconductor technological progress: the industrial focus shifts from how tiny transistors can be manufactured to how fast the whole computing system can respond.

For the global industrial chain, this paradigm diversifies technological development options. Enterprises no longer have to participate in fierce advanced process competition relying on high-end lithography equipment. Advanced packaging, chip architecture innovation and software-hardware co-design become core competitive advantages, offering emerging market participants a feasible breakthrough route.

This innovative technological direction requires open global collaboration. From academic research to industrial technical verification, researchers, engineers and enterprises from all regions can jointly polish relevant theories, iterate technical solutions, and build a more diversified, resilient and sustainable global semiconductor industrial ecosystem.